技術文件
規格
Brand
MicrochipProduct Type
Microcontroller
Series
PIC16C62X
Package Type
SOIC
Pin Count
18
Device Core
PIC
Data Bus Width
8bit
Program Memory Size
1.75kB
Maximum Clock Frequency
40MHz
RAM Size
128bit
Maximum Supply Voltage
6V
Number of Programmable I/Os
13
Minimum Operating Temperature
-40°C
Analogue Comparators
2
Maximum Operating Temperature
85°C
Standards/Approvals
No
Minimum Supply Voltage
2.5V
Number of Timers
1
Instruction Set Architecture
Harvard
Automotive Standard
No
ADCs
10 bit
Program Memory Type
OTP
產品詳情
The Microchip microcontroller is 18 pin ROM/ EPROM based members of the versatile PICmicro® family of low cost, high performance, CMOS, fully static, 8 bit microcontrollers. The PICmicro microcontroller employ an advanced RISC architecture. This devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8 bit wide data.
暫時無法取得庫存資訊。
1,158.60 MOP
27.586 MOP Each (In a Tube of 42) (不含稅)
42
1,158.60 MOP
27.586 MOP Each (In a Tube of 42) (不含稅)
暫時無法取得庫存資訊。
42
| 數量 | 單價 | 每管子 |
|---|---|---|
| 42 - 168 | 27.586 MOP | 1,158.59 MOP |
| 210+ | 27.033 MOP | 1,135.40 MOP |
技術文件
規格
Brand
MicrochipProduct Type
Microcontroller
Series
PIC16C62X
Package Type
SOIC
Pin Count
18
Device Core
PIC
Data Bus Width
8bit
Program Memory Size
1.75kB
Maximum Clock Frequency
40MHz
RAM Size
128bit
Maximum Supply Voltage
6V
Number of Programmable I/Os
13
Minimum Operating Temperature
-40°C
Analogue Comparators
2
Maximum Operating Temperature
85°C
Standards/Approvals
No
Minimum Supply Voltage
2.5V
Number of Timers
1
Instruction Set Architecture
Harvard
Automotive Standard
No
ADCs
10 bit
Program Memory Type
OTP
產品詳情
The Microchip microcontroller is 18 pin ROM/ EPROM based members of the versatile PICmicro® family of low cost, high performance, CMOS, fully static, 8 bit microcontrollers. The PICmicro microcontroller employ an advanced RISC architecture. This devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8 bit wide data.