技術文件
規格
Brand
MicrochipSeries
PIC16C62X
Product Type
Microcontroller
Package Type
SOIC
Pin Count
18
Device Core
PIC
Data Bus Width
8bit
Program Memory Size
1.75kB
Maximum Clock Frequency
40MHz
RAM Size
128bit
Maximum Supply Voltage
6V
Number of Programmable I/Os
13
Minimum Operating Temperature
-40°C
Analogue Comparators
2
Maximum Operating Temperature
85°C
Standards/Approvals
No
Minimum Supply Voltage
2.5V
Automotive Standard
No
ADCs
10 bit
Program Memory Type
OTP
Number of Timers
1
Instruction Set Architecture
Harvard
產品詳情
The Microchip microcontroller is 18 pin ROM/ EPROM based members of the versatile PICmicro® family of low cost, high performance, CMOS, fully static, 8 bit microcontrollers. The PICmicro microcontroller employ an advanced RISC architecture. This devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8 bit wide data.
暫時無法取得庫存資訊。
27.50 MOP
27.51 MOP Each (Supplied in a Tube) (不含稅)
生產包 (管子)
1
27.50 MOP
27.51 MOP Each (Supplied in a Tube) (不含稅)
暫時無法取得庫存資訊。
生產包 (管子)
1
| 數量 | 單價 |
|---|---|
| 1 - 4 | 27.51 MOP |
| 5 - 9 | 26.90 MOP |
| 10+ | 26.48 MOP |
技術文件
規格
Brand
MicrochipSeries
PIC16C62X
Product Type
Microcontroller
Package Type
SOIC
Pin Count
18
Device Core
PIC
Data Bus Width
8bit
Program Memory Size
1.75kB
Maximum Clock Frequency
40MHz
RAM Size
128bit
Maximum Supply Voltage
6V
Number of Programmable I/Os
13
Minimum Operating Temperature
-40°C
Analogue Comparators
2
Maximum Operating Temperature
85°C
Standards/Approvals
No
Minimum Supply Voltage
2.5V
Automotive Standard
No
ADCs
10 bit
Program Memory Type
OTP
Number of Timers
1
Instruction Set Architecture
Harvard
產品詳情
The Microchip microcontroller is 18 pin ROM/ EPROM based members of the versatile PICmicro® family of low cost, high performance, CMOS, fully static, 8 bit microcontrollers. The PICmicro microcontroller employ an advanced RISC architecture. This devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8 bit wide data.